Intel：2009年32nm工艺采用3D晶体管技术

.Dkc166 制造工艺的革新总是Intel的强项之一。为了进一步提高处理器性能、降低功耗、增加弹性，Intel计划在2009年的32nm工艺中采用“3D晶体管(三门晶体管)”技术，据称可将芯片的功耗降低35％之多。

Intel此前已经多次提高3D晶体管技术，而在夏威夷火奴鲁鲁的超大规模集成电路技术讨论会上，Intel透露了更多技术细节，并首次公布了一些数据资料。

Intel研发副总裁Mike Mayberry表示，与目前的平面晶体管技术不同，3D晶体管技术使用了三个“门”(打开和关闭晶体管的开关)，而不是一个，新增的两个门可以增加通过晶体管的电流，并减少泄漏。Mayberry称，Intel已经采用65nm技术生产出了第一个3D晶体管，相比之下可提速45％，金属氧化物半导体处于关闭状态下的电流也减少50％，芯片的总体功耗可由此降低35％。

随着晶体管数量每18-24个月翻一番，同时更多的芯片要不停地开启和关闭，50％的电流减少无疑将为移动设备带来福音，拥有更好的电池续航能力。

Mayberry还强调说，3D晶体管只是Intel研发中用于改进生产工艺的众多新技术之一。

Intel表示，Intel已经接近在一颗芯片上整合10亿个3D晶体管的程度，有望在2009年年底部署的32nm工艺上实现批量生产。如果效果能符合预期，Intel将在所有的半导体产品上推广这一新技术。
有点像硬盘的垂直技术
终于从平面走向立体了.
确实很有意思。
我打算2015年换电脑……
Intel considers 3D transistors for 32 nm processors

Honolulu (Hawaii) - Intel is going to great lengths to get a better handle on the power consumption of its semiconductors. On step closer to reality is the "tri-gate" transistor, which enables the company to gain more flexibility in adjusting, processor performance and power consumption. The technology could be available by 2009 and drop a chip's total power by 35%, Intel said.

The tri-gate transistor isn't entirely a new announcement, as the company has been talking about the technology at various events since September of 2002. Presenting at the 2006 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, Intel followed up with more details and first test results, which indicated that the tri-gate transistor, often also referred to as "3D transistor" may in fact be a technology that will make it into production one day. ;
Intel's approach to enhance the gate technology in transistors tackles one of the major concerns especially in micro processors. Transistor gates consist of a gate electrode and gate dielectric. Both components control the flow of electrons between the source and drain by switching on and off the main current. Shrinking the structures of transistors has created several challenges such as increasing current leakage in "off" states of a transistor - causing the overall power consumption of a semiconductor device to climb.

While Intel has found solutions to keep the traditional gate architecture alive through the introduction of strained silicon to enhance electron flow and a so called "high-K" gate material in place of silicon dioxide to reduce current leakage, additional shrinks may require completely new approaches to control leakage and improve transistor performance. One possible solution could be tri-gate transistors, Intel believes.

Compared to today's planar transistors, tri-gate transistors use three gates instead of only one. According to Mike Mayberry, vice president and director of component research at Intel, the addition of two gates allows the company to increase the amount of current running through the transistor and decrease leakage since current can be routed into three different channels. First tri-gate transistors apparently have been manufactured and Mayberry claimed that 65 nm versions offer a 45% increase in speed or 50x reduction in "off"-current when compared to regular planar transistors.

If Intel can transfer these numbers into greater amounts of transistors, it isn't hard to imagine that tri-gate technology will become more and more important over time: With the amount of transistors doubling every 18 - 24 months and a growing flexibility to turn more parts of a micro chip on and off, a 50% reduction of off-current could deliver a whole new range of mobile devices and bring us closer to those notebooks with 8 hours battery time. www.dngz.net

An even better solution than tri-gate transistor would be a pipe-structure, with a single gates and completely surrounding the electron flow from source to drain. However, this would require Intel to create a "tunnel" for the main current, which - according to Mayberry - is still science fiction. "At least today we cannot manufacture such a model," he mentioned in a conference call. However, he did not rule out that future technologies could provide an opportunity to develop such a transistor.

The executive stressed that tri-gate technology is "only one" approach to control performance and leakage in production processes down the road. But even if tri-gate is barely more than a research project - Mayberry said that Intel is "nowhere near to build 1 billion tri-gate transistors onto one chip - it appears to make steady progress and not be one of Intel's countless research projects that don't make it past a scientific paper presentation.

Mayberry indicated that a mass-production of the tri-gate transistor would be possible "with the 32nm chip generation," which is expected to debut at the end of 2009. If adapted, he expects the technology to move across all semiconductor products built by Intel.
鹰格力屎……